1. Field of the Invention
The present invention relates to a memory, and more particularly, to a non-volatile memory and a method for fabricating the same.
2. Description of the Related Art
The non-volatile memory is characterized by maintaining the stored data even when the power is down, and has thus become a mandatory device in many electronic products for providing normal operation of the electronic products when booted. Thus, the non-volatile memory has been widely used device in personal computer (PC) and other electronic equipment.
In a conventional non-volatile memory, a stacked layer made of oxide-nitride-oxide (ONO layer) is disposed between a gate and a substrate. Wherein, the nitride layer, used as a film layer where the charges are trapped in, is also known as a charge trapping layer, and the memory cell, whose charge trapping layer is made of such material, is called Nitride Read Only Memory.
FIG. 1 schematically shows a cross-sectional view of a conventional nitride read only memory. Referring to FIG. 1, the nitride read only memory comprises a substrate 100, a source 102, a drain 104, a bottom silicon oxide layer 106, a nitride layer 108, a top silicon oxide layer 110, and a gate 112. Wherein, the bottom silicon oxide layer 106, the nitride layer 108, and the top silicon oxide layer 110, which are all disposed on the substrate 100, form an oxide-nitride-oxide stacked layer, the so-called ONO layer 114. In addition, the larger dotted circle shown in the diagram indicates a memory cell 116, and the smaller dotted circles indicate a first bit 118 and a second bit 120, respectively. Regarding to the memory cell 116, a memory cell can basically store one bit (first bit 118 and second bit 120) at the two side of the nitride layer 108 of the ONO layer 114 near the drain 104 and the source 102, respectively, thereby forming a single memory cell 2 bits/cell non-volatile memory.
However, when programming a conventional 2 bits non-volatile memory, two bits in the same memory cell are conditioned by each other, which may cause problems. In other words, if a bit (the second bit 120) has been stored in a portion near the drain 104, a 2nd-bit effect occurs when the process of reverse read is performed, such that the voltage in the portion where a high current is expected may drop. That is, when the memory cell is being read, the existing bit may have direct impact on the memory cell, thus increasing the barrier and the threshold voltage (Vt) for reading. In addition, the cross interference of two bits in the single memory cell mentioned above may substantially implicate the device operation and even deteriorate the device reliability.
Moreover, when programming the conventional 2 bits non-volatile memory, the hot electrons injected into the electron trapping layer may form an electron distribution curve according to the injected energy. However, the 2nd-bit effect mentioned above cause the charge distribution curve to be wider and the curves to overlap. Therefore, when erasing the memory cell, the distribution curve formed when injecting the hot electrons into the charge trapping layer can not match with the electron distribution curve, thus the erasing will take more time and worse, the whole content of the memory cell may not be totally erased.